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ad10242 features 2 matched adcs with input signal conditioning selectable bipolar input voltage range ( 0.5 v, 1.0 v, 2.0 v) full mil-std-883b compliant 80 db spurious-free dynamic range trimmed channel-channel matching applications radar processing communications receivers flir processing secure communications any i/q signal processing application the ad10242 operates with 5.0 v for the analog signal condi- t ioning with a separate 5.0 v supply for the analog-to-digital c onversion. each channel is completely independent, allowing operation with independent encode or analog inputs. the ad10242 also offers the user a choice of analog input signal ranges to mini- mize additional signal conditioning required for multiple functions within a single system. the heart of the ad10242 is the ad9042, which is designed s pecifically for applications requiring wide dynamic range. the ad10242 is manufactured on analog devices mil-prf-38534 mcm line and is completely qualified. units are packaged in a custom, cofired, ceramic 68-lead gull wing package and specified for operation from ?5 c to +125 c. contact the factory for additional custom options including those that allow the user to ac couple the adc directly, bypassing the front end amplifier section. also see the ad9042 data sheet for additional details on adc performance. product highlights 1. guaranteed sample rate of 40 msps. 2. dynamic performance specified over entire nyquist band; spurious signals @ 80 dbc for ? dbfs input signals. 3. low power dissipation: <2 w off 5.0 v supplies. 4. user defined input amplitude. 5. packaged in 68-lead ceramic leaded chip carrier. general description the ad10242 is a complete dual signal chain solution including on-board amplifiers, references, adcs, and output buffering pro viding unsurpassed total system performance. each channel is laser t rimmed for gain and offset matching and provides channel- to-channel crosstalk performance better than 80 db. the ad10242 utilizes two each of the ad9632, op279, and ad9042 in a cus- tom mcm to gain space, performance, and cost advantages over solutions previously available. functional block diagram op279 op279 ad9042 ad9632 9 12 timing a in 3 a in 2a in 1 d11b (msb) d10b d9b d8b d7b d0b (lsb) d1b d2b d3b d4b d5b d6b d9a d10a d11a (msb) (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a enc ad10242 5 v ref output buffering uneg ucom upos op279 op279 ad9042 ad9632 7 12 timing a in 2 a in 1 v ref output buffering a in 3 upos uneg ucom enc enc enc dual, 12-bit, 40 msps mcm a/d converter with analog input signal conditioning a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc. all rights reserved. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. rev. d 2015 781/461-3113
ad10242* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad10242 evaluation board documentation application notes ? an-297: test video a/d converters under dynamic conditions data sheet ? ad10242 military data sheet ? ad10242: dual, 12-bit, 40 msps mcm a/d converter with analog input signal conditioning data sheet software and systems requirements ? military part cross-reference guide ? military products by function ? military products by generic part number ? smd to generic cross reference reference materials technical articles ? class t satellite products ? correlating high-speed adc performance to multicarrier 3g requirements ? dnl and some of its effects on converter performance ? ms-2210: designing power supplies for high speed adc ? multi-channel analog-to-digital converter module integration design resources ? ad10242 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad10242 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
? ad10242?pecifications electrical characteristics (av cc = +5 v; av ee = ?.0 v; dv cc = +5 v; applies to each adc, unless otherwise noted.) test mil ad10242bz/tz parameter temp level subgroup min typ max unit resolution 12 bits dc accuracy no missing codes full vi 1, 2, 3 guaranteed offset error 25 ci 1 ?.5 0.05 +0.5 % fs full vi 2, 3 ?.0 1.0 +2.0 % fs offset error channel match full v 0.1 % gain error 1 25 ci 1 ?.0 0.5 +1.0 % fs full vi 2, 3 ?.5 0.8 +1.5 % fs gain error channel match full v 0.1 % analog input (a in ) input voltage range a in 1 full i 0.5 v a in 2 full i 1.0 v a in 3 full i 2v input resistance a in 1 full iv 12 99 100 101 ? a in 2 full iv 12 198 200 202 ? a in 3 full iv 12 396 400 404 ? input capacitance 2 25 civ 12 0 4.0 7.0 pf analog input bandwidth 3 full v 60 mhz encode input 4, 5 logic compatibility ttl/cmos logic ??voltage full i 1, 2, 3 2.0 5.0 v logic ??voltage full i 1, 2, 3 0 0.8 v logic ??current (v inh = 5 v) full i 1, 2, 3 625 800 a logic ??current (v inl = 0 v) full i 1, 2, 3 ?00 ?00 a input capacitance 25 cv 12 7.0 pf switching performance maximum conversion rate 6 full vi 4, 5, 6 40 50 msps minimum conversion rate 6 full v 12 5 msps aperture delay (t a )2 5 cv 1.0 ns aperture delay matching 25 cv 2.0 ns aperture uncertainty (jitter) 25 cv 1 ps rms encode pulsewidth high 25 civ 12 12 10 ns encode pulsewidth low 25 civ 12 10 41 ns output delay (t od ) full iv 12 10 12 14 ns snr 7 analog input @ 1.2 mhz 25 cv 68 db @ 4.85 mhz 25 ci 4 63 66 db full ii 5, 6 62 66 db @ 9.9 mhz 25 ci 4 63 65 db full ii 5, 6 62 65 db @ 19.5 mhz 25 ci 4 60 63 db full ii 5, 6 59 62 db sinad 8 analog input @ 1.2 mhz 25 cv 67 db @ 4.85 mhz 25 ci 4 62 65 db full ii 5, 6 61 64 db @ 9.9 mhz 25 ci 4 60 64 db full ii 5, 6 60 63 db @ 19.5 mhz 25 ci 4 58 61 db full ii 5, 6 58 60 db rev. d
test mil ad10242bz/tz parameter temp level subgroup min typ max unit spurious-free dynamic range 9 analog input @ 1.2 mhz 25 ci 81 dbfs @ 4.85 mhz 25 ci 47 080 dbfs full ii 5, 6 70 79 dbfs @ 9.9 mhz 25 ci 46 370 dbfs full ii 5, 6 63 69 dbfs @ 19.5 mhz 25 ci 46 067 dbfs full ii 5, 6 60 66 dbfs two-tone imd rejection 10 f1, f2 @ ? dbfs full ii 4, 5, 6 70 76 dbc channel-to- channel isolation 11 25 civ12 75 80 db transient response 25 cv 10 ns linearity differential nonlinearity 25 civ12 0.3 1.0 lsb (encode = 20 mhz) full iv 12 0.5 1.25 lsb integral nonlinearity 25 cv 0.3 lsb ( encode = 20 mhz) full v 0.5 lsb overvoltage recovery time 12 v in = 2.0 fs full iv 12 50 100 ns v in = 4.0 fs full iv 12 75 200 ns digital outputs logic compatibility cmos logic ??voltage 13 full i 1, 2, 3 3.5 4.2 v logic ??voltage 14 full i 1, 2, 3 0.45 0.65 v output coding twos complement power supply av cc supply voltage full vi 5.0 v i (av cc ) current full v 260 ma av ee supply voltage full vi ?.0 v i (av ee ) current full v 55 ma dv cc supply voltage full vi 5.0 v i (dv cc ) current full v 25 ma i cc (total) supply current full i 1, 2, 3 350 400 ma power dissipation (total) full i 1, 2, 3 1.75 2.0 w power supply rejection ratio (psrr) full i 7, 8 0.01 0.02 % fsr/% v s pass-band ripple to 10 mhz full iv 12 0.2 db notes 1 gain tests are performed on a in 3 over specified input voltage range. 2 input capacitance specifications combine ad9632 die capacitance and ceramic package capacitance. 3 full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. 4 encode driven by single-ended source; encode bypassed to ground through 0.01 f capacitor. 5 encode may also be driven differentially in conjunction with encode ; see encoding the ad10242 section for details. 6 minimum and maximum conversion rates allow for variation in encode duty cycle of 50% 5%. 7 analog input signal power at ? dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first five harmonics removed). encode = 40.0 msps. 8 analog input signal power at ? dbfs; signal-to-noise and distortion (sinad) is the ratio of signal level to total noise + harmonics. encode = 40.0 msps. 9 analog input signal equals ? dbfs; sfdr is the ratio of converter full scale to worst spur. 10 both input tones at ? dbfs; two-tone intermodulation distor tion (imd) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 mhz 100 khz, 50 khz f1 ?f2 300 khz. 11 channel-to-channel isolation tested with a channel grounded and a full-scale signal applied to b channel (a in 1). 12 input driven to 2 and 4 a in 1 range for >4 clock cycles. output recovers in band in specified time with encode = 40 msps. no foldover guaranteed. 13 outputs are sourcing 10 a. 14 outputs are sinking 10 a. all specifications guaranteed within 100 ms of initial power-up regardless of sequencing. specifications subject to change without notice. ad10242 ? rev. d
ad10242 ? absolute maximum ratings 1 parameter min max unit electrical v cc voltage 0 7 v v ee voltage ? 0 v analog input voltage v ee v cc v analog input current ?0 +10 ma digital input voltage (encode) 0 v cc v e ncode, encode differential voltage 4 v digital output current ?0 +40 ma environmental 2 operating temperature (case) ?5 +125 c maximum junction temperature 175 c l ead temperature (soldering, 10 sec) 300 c storage temperature range (ambient) ?5 +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances for es-68-1 package: jc = 11 c/w; ja = 30 c/w. table i. output coding msb lsb base 10 input 0111111111111 2047 +fs 0000000000001 +1 0000000000000 0 0.0 v 1111111111111 ?, 4095 1000000000000 ?047, 2048 ?s explanation of test levels test level i 100% production tested. ii 100% production tested at 25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi all devices are 100% production tested at 25 c; sample tested at temperature extremes. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad10242 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device rev. d
ad10242 ? 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 1 8765 6766 65 64 63 62 432168 pin 1 identifier top view (not to scale) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 nc = no connect ad10242 gnda gnda uposa av ee av cc nc nc (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a gnda gnda encodea encodea dv cc d9a d10a (msb) d11a nc nc (lsb) d0b d1b d2b d3b d4b d5b d6b gndb gndb gndb gndb uposb unegb ucomb gndb gndb encodeb encodeb dv cc d11b (msb) d10b d9b d8b d7b gndb gnda a in a3 a in a2 a in a1 gnda ucoma unega gnda shield gndb av ee av cc gndb a in b3 a in b2 a in b1 gndb pin configuration 68-lead ceramic leaded chip carrier pin function descriptions pin no. mnemonic function 1 shield internal ground shield between channels. 2, 5, 9?1, 26?7 gnda a channel ground. a and b grounds should be connected as close to the device as possible. 3 unega unipolar negative. 4 ucoma unipolar common. 6a in a1 analog input for a side adc (nominally 0.5 v). 7a in a2 analog input for a side adc (nominally 1.0 v). 8a in a3 analog input for a side adc (nominally 2.0 v). 12 uposa unipolar positive. 13 av ee analog negative supply voltage (nominally ?.0 v or ?.2 v). 14 av cc analog positive supply voltage (nominally 5.0 v). 15, 16, 34, 35 nc no connect. 17?5, 31?3 d0a?11a digital outputs for adc a. (d0 lsb.) 28 encodea encode is the complement of encode. 29 encodea data conversion is initiated on the rising edge of the encode input. 30, 50 dv cc digital positive supply voltage (nominally 5.0 v). 36?2, 45?9 d0b?11b digital outputs for adc b. (d0 lsb.) 43?4, 53?4, gndb b channel ground. a and b grounds should be connected as close to the device 58?1, 65, 68 as possible. 51 encodeb data conversion is initiated on the rising edge of the encode input. 52 encodeb encode is the complement of encode. 55 ucomb unipolar common. 56 unegb unipolar negative. 57 uposb unipolar positive. 62 a in b1 analog input for b side adc (nominally 0.5 v). 63 a in b2 analog input for b side adc (nominally 1.0 v). 64 a in b3 analog input for b side adc (nominally 2.0 v). 66 av cc analog positive supply voltage (nominally 5.0 v). 67 av ee analog negative supply voltage (nominally ?.0 v or ?.2 v). rev. d
ad10242 ? overvoltage recovery time t he amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified pe rcentage of full scale is reduced to midscale. power supply rejection ratio t he ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise and distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. signal-to-noise ratio (snr, without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) t he ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. sfdr may be reported in dbc (i.e., degrades as signal levels are lowered) or in dbfs (always r elated back to converter full scale). transient response t he time required for the converter to achieve 0.02% accu- racy when a one-half full-scale step function is applied to the analog input. two-tone intermodulation distortion rejection t he ratio of the rms value of either input tone to the rms value of the w orst third order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of t he peak spurious component. the peak spurious component may or may not be an imd product. two-tone sfdr may be reported in dbc (i.e., degrades as signal levels are lowered) or in dbfs (always related back to converter full scale). definition of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the e ncode pulse should be left in logic ??state to achieve rated perfor mance; pulsewidth low is the minimum time that the encode pulse should be left in low state. at a given clock rate, these specifications define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude to the rms value of the worst harmonic component. integral nonlinearity t he deviation of the transfer function from a reference line measured in fractions of 1 lsb using a ?est straight line?deter- mined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal f requency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between the 50% point of the rising edge of the en code c ommand and the time when all output data bits are within valid logic levels. rev. d
ad10242 ? enc d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1/2 ad10242 shown ttl clock f 10mhz all 5v supply pins bypassed to gnd with a 0.1 f capacitor a in 3 a in 2 a in 1 enc figure 2. equivalent burn-in circuit a in encode n n ?2 n + 2 n + 3 n + 4 n + 5 t a = 1.0ns typ t od = 12ns typ n + 1 n ?1 n n + 1 n + 2 digital outputs figure 1. timing diagram equivalent circuits a in 3 r4 200 a in 2 a in 1 to ad9632 r3 100 r2 21 r1 79 figure 3. analog input stage timing circuits encode encode av cc av cc r1 17k r2 8k r2 8k r1 17k av cc figure 4. encode inputs dv cc v ref dv cc current mirror current mirror d0?11 figure 5. digital output stage rev. d
? ad10242?ypical performance characteristics frequency ?mhz 0 power relative to full scale ?db ?0 ?00 020 24681012141618 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 40msps a in = 4.85mhz a in = ?dbfs snr = 66.4db sfdr = 72.8dbc tpc 1. single tone @ 4.85 mhz frequency ?mhz 0 ?0 ?00 0 20 24681012141618 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 40msps a in = 9.9mhz a in = ?dbfs snr = 66.0db sfdr = 65.7dbc power relative to full scale ?db tpc 2. single tone @ 9.9 mhz frequency ?mhz 0 power relative to full scale ?db ?0 ?00 0 20 24681012141618 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 40msps a in = 19.5mhz a in = ?dbfs snr = 64.3db sfdr = 63.3dbc tpc 3. single tone @ 19.5 mhz frequency ?mhz power relative to full scale ?db 0 ?0 ?00 020 2468101 2141618 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 40msps a in 1 = 9.8mhz a in 1 = ?dbfs a in 2 = 10.1mhz a in 2 = ?dbfs sfdr = 76.0dbc tpc 4. two-tone fft @ 9.8 mhz/10.1 mhz frequency ?mhz power relative to full scale ?db 0 ?0 ?00 020 24681012141618 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 40msps a in 1 = 19.5mhz a in 1 = ?dbfs a in 2 = 19.7mhz a in 2 = ?dbfs sfdr = 70.6dbc tpc 5. two-tone fft @ 19.5 mhz/19.7 mhz analog input frequency ?mhz 66 58 520 10 76 68 64 60 72 70 62 74 encode = 40msps a in = ?dbfs t = +125 c t = +25 c t = ?5 c worst-case harmonic ?db tpc 6. harmonics vs. a in rev. d
ad10242 ? analog input frequency ?mhz 64.0 61.5 520 10 67.0 64.5 63.0 66.0 65.0 62.0 encode = 40msps a in = ?dbfs t = +125 c t = +25 c t = ?5 c 62.5 63.5 65.5 snr ?db 66.5 tpc 7. snr vs. a in sample rate ?msps 70 58 550 10 66 62 a in = 9.9mhz a in = ?dbfs sfdr 64 68 60 snr, worst spur ?db, dbc 15 20 25 30 35 40 45 snr tpc 8. snr and harmonics vs. encode rate temperature ? c ?.0 ?5 125 gain 25 offset 45 65 85 105 5?5 ?5 ?.5 ?.0 ?.5 0 0.5 1.0 1.5 2.0 error ?% fs tpc 9. offset and gain error vs. temperature analog input frequency ?mhz ?0 10 in a1 25 30 35 40 20 15 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 encode = 40msps a in = ?dbfs isolation ?db in b1 in b3 in a3 tpc 10. isolation vs. frequency analog input power level ?dbfs 60 0 ?0 ?0 40 20 encode = 40msps a in = 9.98mhz sfdr (dbfs) 30 50 10 ?0 ?0 ?0 ?0 ?0 0 70 80 90 sfdr (dbc) sfdr = 75db worst-case spurious ?dbc, dbfs tpc 11. single tone sfdr (a in @ 9.98) vs. power level analog input power level ?dbfs 60 0 ?0 ?0 40 20 encode = 40msps a in = 19.9mhz sfdr (dbfs) 30 50 10 ?0 ?0 ?0 ?0 ?0 0 70 80 90 sfdr (dbc) sfdr = 75db 100 worst-case spurious ?dbc, dbfs tpc 12. single tone sfdr (a in @ 19.9) vs. power level rev. d
ad10242 ?0 theory of operation refer to the functional block diagram. the ad10242 employs three monolit hic adi components per channel (ad9632, op279, and a d9042), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit ana log-to-digital converter. the input signal is first passed through a precision laser trimmed resistor divider, allowing the user to externally select operation with a full-scale signal of 0.5 v, 1.0 v, or 2.0 v by choosing t he proper input terminal for the application. the result of the resistor div ider is to apply a full-scale input of approximately 0.4 v to the noninverting input of the internal ad9632 amplifier. the ad9632 provides the dc-coupled level shift circuit required for operation with the ad9042 adc. configuring the amplifier in a noninverting mode, the ac signal gain can be trimmed to provide a constant input to the adc centered around the inter- nal reference voltage of the ad9042. this allows the converter to be used in multiple system applications without the need for external gain and level shift circuitry normally requiring trim. t he ad9632 was chosen for its superior ac performance and in put drive capabilities. these two specifications have limited the ability of many amplifiers to drive high performance adcs. as new amplifiers are developed, pin compatible improve- ments are planned to in corporate the latest operational ampli- fier technology. the op279 provides the buffer and inversion of the internal ref erence of the ad9042 in order to supply the summing node of the ad9632 input amplifier. this dc voltage is then summed with the input voltage and applied to the input of the ad9042 adc. the reference voltage of the ad9042 is designed to track i nternal offsets and drifts of the adc and is used to ensure matching over an extended temperature range of operation. applying the ad10242 encoding the ad10242 t he a d10242 is designed to interface with ttl and cmos l ogic families. the source used to drive the encode pin(s) must be clean and free from jitter. sources with excessive jitter will limit snr and overall performance. 0.01f ttl or cmos source encode encode ad10242 figure 6. single-ended ttl/cmos encode the ad10242 encode inputs are connected to a differential in put stage (see figure 4). with no input connected to either th e encode or encode input, the voltage dividers bias the inputs to 1.6 v. for ttl or cmos usage, the encode source should be connected to encode (pins 29 and/or 51). encode (pins 28 and/or 52) should be decoupled using a low inductance or microwave chip capacitor to ground. devices such as avx 05085c103ma15, a 0.01 f capacitor, work well. performance improvements it is possible to improve the performance of the ad10242 slightly by taking advantage of the internal characteristics of the amplifier and converter combination. by increasing the 5 v su pply slightly, the user may be able to gain up to a 5 db improve- men t in sfdr over the entire frequency range of the converter. it is not recommended to exceed 5.5 v on the analog supplies since there are no performance benefits beyond that range and care should be taken to avoid the absolute maximum ratings. analog input frequency ?mhz 60 0 510 40 20 encode = 40msps a in = 1dbfs snr (db) 30 50 10 20 29.2 34.5 52.5 60.95 70 80 sfdr (dbfs) snr, worst spur ?db, dbc tpc 13. snr/harmonics to a in > nyquist msps input frequency ?mhz 0.5 3.0 05 2.0 1.5 1.0 2.5 10 15 20 25 30 40 0 ?.5 45 50 55 35 fundamental levels ?dbfs encode = 40msps tpc 14. gain flatness vs. input frequency rev. d
ad10242 ?1 if a logic threshold other than the nominal 1.6 v is required, the following equations show how to use an external resistor, rx, to raise or lower the trip point (see figure 4, r1 = 17 k ? , r2 = 8 k ? ). v rrx rr rrx r rx 1 52 12 1 2 = ++ to lower logic threshold. 0.01f encode source encode encode ad10242 r x v l 5v r1 r2 figure 7. lower threshold for encode v r r rrx rrx 1 52 2 1 1 = + + to raise logic threshold. 0.01f encode source encode encode ad10242 r x v l 5v r1 r2 av cc figure 8. raise logic threshold for encode while the single-ended encode will work well for many applica- tio ns, driving the encode differentially will provide increased performance. depending on circuit layout and system noise, a 1 db to 3 db improvement in snr can be realized. it is recom- mended that the encode signal be a c-coupled into the encode and encode pins. the simplest option is shown below. the low jitter ttl signal is c oupled with a limiting resistor, typically 100 ? , to the primary side of an rf transformer (these transformers are inexpensive a nd readily available; part number in figures 9 and 10 is from mini-circuits). the se condary side is connected to the encode and encode pins of the converter. since both encode inputs are self-biased, no additional components are required. ttl encode encode ad10242 100 t1?t figure 9. ttl source?ifferential encode if no ttl source is available, a clean sine wave may be substi- tut ed. in the case of the sine source, the matching network is shown below. since the matching transformer specified is a 1:1 i mpedance ratio, the load resistor r should be selected to match the source impedance. the input impedance of the ad 9042 is negligible in most cases. encode encode ad10242 r t1?t sine source figure 10. sine source?ifferential encode if a low jitter ecl clock is available, another option is to ac-couple a differential ecl signal to the encode input pins, as shown in figure 11. the capacitors shown here should be chip capaci- tors but do not need to be of the low inductance variety. encode encode ad10242 ecl gate 0.1f 0.1f ? s 510 510 figure 11. differential ecl for encode as a final alternative, the ecl gate may be replaced by an ecl comparator. the input to the comparator could then be a logic signal or a sine signal. encode encode ad10242 0.1f 0.1f ? s 50 ad96687 (1/2) 510 510 figure 12. ecl comparator for encode care should be taken not to overdrive the encode input pin when ac-coupled. although the input circuitry is electrically protected from overvoltage or undervoltage conditions, improper circuit operations may result from overdriving the encode input pin. rev. d
ad10242 ?2 using the flexible input the ad10242 has been designed with the user? ease of opera- tion in mind. multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. while the standard inputs are 0.5 v, 1.0 v, and 2.0 v, the user can select the input impedance of the ad10242 on any input by using the other inputs as alternate locations for gnd or an external resistor. the following chart summarizes the impedance options available at each input location: a in 1 = 100 ? when a in 2 and a in 3 are open. a in 1 = 75 ? when a in 3 is shorted to gnd. a in 1 = 50 ? when a in 2 is shorted to gnd. a in 2 = 200 ? when a in 3 is open. a in 2 = 100 ? when a in 3 is shorted to gnd. a in 2 = 75 ? when a in 2 to a in 3 has an external resistor of a in 2 = 300 ? , with a in 3 shorted to gnd. a in 2 = 50 ? when a in 2 to a in 3 has an external resistor of a in 2 = 100 ? , with a in 3 shorted to gnd. a in 3 = 400 ? . a in 3 = 100 ? when a in 3 has an external resistor of 133 ? to gnd. a in 3 = 75 ? when a in 3 has an external resistor of 92 ? to gnd. a in 3 = 50 ? when a in 3 has an external resistor of 57 ? to gnd. while the analog inputs of the ad10242 are designed for dc- coupled bipolar inputs, the ad10242 has the ability to use unipolar inputs in a user selectable mode through the addi- tion of an external resistor. this allows for 1 v, 2 v, and 4 v full-scale unipolar signals to be applied to the various inputs (a in 1, a in 2, and a in 3, respectively). placing a 2.43 k ? resis- tor (typical, off set calibration required) between upos and ucom shifts the reference voltage setpoint to allow a unipolar positive volt age to be applied at the inputs of the device. to cali- brate offset, apply a midscale dc voltage to the converter while adjusting the unipolar resistor for a midscale output transition. a in 2 upos ad10242 2.43k ucom a in 3 a in 1 figure 13. unipolar positive to operate with ? v, ? v, or ? v full-scale unipolar signals, place a 2.67 k ? resistor (typical, offset calibration required) between uneg and ucom. this again shifts the reference volt- age setpoint to allow a unipolar negative voltage to be applied at the inputs of the device. to calibrate offset, apply a midscale dc voltage to the converter while adjusting the unipolar resistor for a midscale output transition. a in 2 uneg ad10242 2.67k ucom a in 3 a in 1 figure 14. unipolar negative grounding and decoupling analog and digital grounding proper grounding is essential in any high speed, high resolution system. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power schemes. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation, and ground plane. these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvement in performance. it is important to design a layout that prevents noise from cou- pling to the input signal. digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. the ad10242 does not distinguish between analog and digital ground pins as the ad10242 should always be treated like an analog component. all ground pins should be connected together directly under the ad10242. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path and manage the power and ground currents. the ground plane should be removed from the area near the input pins to reduce stray capacitance. layout information the schematic of the evaluation board (figure 15) represents a typical implementation of the ad10242. the pinout of the ad10242 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. it is recommended that high quality ceramic chip c apacitors be used to decouple each supply pin to ground directly at the device. all capacitors except the one placed on encode can be standard high quality ceramic chip capacitors. the capacitor used on the encode pin must be a low induc- tance chip capacitor as referenced previously. rev. d
ad10242 ?3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 96 1 8765 68676665646362 4321 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 dut ad10242 d0a d11b a in a3 a in a2 a in a1 a in b3 a in b2 a in b1 gnd gnd gnd gnd gnd tp5 tp6 gnd gnd d1a d2a d3a d4a d5a d6a d7a d8a d10b d9b d8b d7b gnd ?.2v +5va gnd gnd gnd gnd gnd gnd gnd tp2 tp3 tp4 gnd gnd encb encb +5vd gnd enca enca +5vd d9a d10a d11a gnd gnd d0b d1b d2b d3b d4b d5b d6b gnd gnd tp1 ?.2v +5va (msbb) d11b d10b d9b d8b d7b gndb gndb gndb gndb uniposb uninegb unicomb gndb gndb encb encb +5vdb d0a (lsba) gnda gnda gnda d1a d2a d3a d4a d5a d6a d7a d8a nca nca uniposa ?.2vaa +5vaa a in a3 a in a2 a in a1 a in b3 a in b2 a in b1 gndb gndb unicoma uninega shield +5vab ?.2vab gnda gnda gnda gnda gndb enca enca +5vda d9a d10a d11a (msba) ncb ncb d0b (lsbb) d1b d2b d3b d4b d5b d6b gndb 5 8 6 3 2 r7 49.9 r3 470 r5 470 vhigh pulse a in u3 ad8036q sma j11 sma j12 pulse a out vlow 5va 5va c1 0.1f 14 u1 k1115 7 8 h2dm j15 h2dm j17 buflata sma jc sma j1 sma ja c14 0.1f r10 470 r9 470 2 3 8 u5 ad9696kn e5 5 7 12 12 a section t1 t1?t 2 1 3 4 6 encab enca 1 : 1 gnd r1 100 v cc out v ee 51 sma j2 a in a1 sma j3 a in a2 sma j4 a in a3 sma j5 a in b1 sma j6 a in b2 sma j7 a in b3 u4 c17 0.1f u3 c18 0.1f dut c9 0.1f c23 10f u5 c12 0.1f u6 c3 0.1f dut c8 0.1f +5vd u3 c15 0.1f u4 c16 0.1f c24 10f u5 c13 0.1f u6 c4 0.1f dut c11 0.1f ?.2v dut c10 0.1f dut c7 0.1f c25 10f dut c6 0.1f +5v vhigh u4 c22 0.1f u3 c21 0.1f vlow u3 c19 0.1f u4 c20 0.1? +5va +5va e1 vhigh vhigh vlow vlow gnd gnd e3 ?.2v ?.2v e2 b jacks tp2 tp2 tp1 tp1 tp3 tp3 tp4 tp4 tp5 tp5 tp7 encab tp6 tp6 tp8 enca tp9 encbb tp10 encb test points +5vd 140 (msb) d11b 239 d10b 338 d8b 536 d9b 437 d7b 635 d6b 734 d4b 932 d5b 833 10 31 11 30 d2b 13 28 d3b 12 29 d1b (lsb) d0b 15 26 gnd 17 24 gnd 16 25 14 27 gnd 18 23 gnd 20 21 gnd 19 22 h40dm j10 buflatb gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 5vd 140 (msb) d11a 239 d10a 338 d8a 536 d9a 437 d7a 635 d6a 734 d4a 932 d5a 833 10 31 buflata 11 30 d2a 128 d3a 12 29 13 d1a (lsb) d0a 15 26 gnd 17 24 gnd 16 25 14 27 gnd 18 23 gnd 20 21 gnd 19 22 h40dm j9 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd e4 5va 5va c2 0.1f 14 u2 k1115 7 8 h2dm j16 h2dm j18 buflatb sma j8 sma jb sma jd c5 0.1f r12 470 r11 470 2 3 8 u5 ad9696kn e5 5 7 12 12 b section out t2 t1?t 2 1 3 4 6 encbb encb 1 : 1 gnd r2 100 51 notes; 1) unipolar operation a side + connect 2.43k res. from tp1 to tp5. a side ?connect 2.67k res. from tp5 to tp6. b side + connect 2.43k res. from tp2 to tp4. b side ?connect 2.67k res. from tp4 to tp3. 2) above unipolar resistor values are nominal and may have to be adjusted depending on offset of dut. 3) encode sources a) for normal operation, a 40mhz ttl clock oscillator is installed in u1 and u2. there is a 51 resistor between j15 and j16. j17 and j18 are open. b) for external square wave encode, input signal at j1 and j8, remove u1, u2, jumpers j15 and j16. connect jumpers j17 and j18. c) for external sine wave encode, input signal at j1 and j8, remove u1, u2, r9, r11, jumpers j15 and j16. connect jumpers j17 and j18. 4) power (5vd) for digital outputs of the ad10242 is supplied via pin 1 of either j9 or j10 (the digital interfaces). to power the eval. board with one 5v supply, jumper a wire from e1 to e4 (connected at factory). 5 8 6 3 2 r8 49.9 r4 470 r6 470 vhigh pulse b in u4 ad8036q sma j13 sma j14 pulse b out vlow v cc v ee figure 15. evaluation board schematic rev. d
ad10242 ?4 care should be taken when placing the digital output runs. because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. internal circuitry buffers the outputs of the ad9042 adc through a resistor network to eliminate the need to externally isolate the device from the receiving gate. evaluation board the ad10242 evaluation board (see figure 16) is designed to provide optimal performance for evaluation of the ad10242 analog-to-digital converter. the board encompasses everything needed to ensure the highest level of performance for evaluating the ad10242. power to the analog supply pins is connected via banana jacks. the analog supply powers the crystal oscillator, the associated co mponents and amplifiers, and the analog section of the ad10242. the digital outputs of the ad10242 are powered via pin 1 of either j9 or j10 found on the digital interface con- nector. to power the evaluation board with one 5 v supply, a jumper wire is required from test point e1 to e4. contact the factory if additional layout or applications assistance is required. figure 16. evaluation board mechanical layout rev. d
ad10242 rev. d | page 15 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are ro unded-off inch equivalents for reference only and are not appropriate for use in design 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) toe down angle 0?8 degrees 0.010 (0.254) 30 0 .050 (1.27) 0.020 (0.508) detail a rotated 90 ccw 1.190 (30.23) 1.180 (29.97) sq 1.170 (29.72) pin 1 10 26 9 61 60 43 27 44 top view (pins down) 0.800 (20.32) bsc 0.960 (24.38) 0.950 (24.13) sq 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.175 (4.45) max 0.235 (5.97) max detail a 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 1.070 (27.18) min 012908- a figure 17. 68-lead ceramic leaded chip carrier [clcc] (es-68-1) dimensions shown in inches and (millimeters) ordering guide model temperature range packag e description package option ad10242bz C40c to +85c 68-lead ceramic leaded chip carrier [clcc] es-68-1 ad10242tz C55c to +125c 68-lead ceramic leaded chip carrier [clcc] es-68-1 ad10242tz/883b C55c to +125c 68-lead ceramic leaded chip carrier [clcc] es-68-1 5962-9581501hxa C55c to +125c 68-lead ceramic leaded chip carrier [clcc] es-68-1 revision history 6/15rev. c to rev. d change to note 2 ............................................................................... 4 updated outline dimensions ........................................................ 15 changes to ordering guide ........................................................... 15 1/03rev. b to rev. c changes to functional block diagram .......................................... 1 changes to table i . ........................................................................... 4 changes to pin function descriptions ........................................... 5 change to encoding the ad10242 section ................................. 10 updated outline dimensions ........................................................ 15 6/01rev. a to rev. b ad9631 references changed to ad9632 ....................... universal ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00665-0-6/15(d)

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